370 lines
10 KiB
ArmAsm
370 lines
10 KiB
ArmAsm
#include "options.h"
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#if !STDLIB
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@--------------------------------------------------------------------------------
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@ DS processor selection
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@--------------------------------------------------------------------------------
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.arch armv5te
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.cpu arm946e-s
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@--------------------------------------------------------------------------------
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#define PAGE_4K (0b01011 << 1)
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#define PAGE_8K (0b01100 << 1)
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#define PAGE_16K (0b01101 << 1)
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#define PAGE_32K (0b01110 << 1)
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#define PAGE_64K (0b00111 << 1)
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#define PAGE_128K (0b10000 << 1)
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#define PAGE_256K (0b10001 << 1)
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#define PAGE_512K (0b10010 << 1)
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#define PAGE_1M (0b10011 << 1)
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#define PAGE_2M (0b10100 << 1)
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#define PAGE_4M (0b10101 << 1)
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#define PAGE_8M (0b10110 << 1)
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#define PAGE_16M (0b10111 << 1)
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#define PAGE_32M (0b11000 << 1)
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#define PAGE_64M (0b11001 << 1)
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#define PAGE_128M (0b11010 << 1)
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#define PAGE_256M (0b11011 << 1)
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#define PAGE_512M (0b11100 << 1)
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#define PAGE_1G (0b11101 << 1)
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#define PAGE_2G (0b11110 << 1)
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#define PAGE_4G (0b11111 << 1)
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#define ITCM_LOAD (1<<19)
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#define ITCM_ENABLE (1<<18)
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#define DTCM_LOAD (1<<17)
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#define DTCM_ENABLE (1<<16)
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#define DISABLE_TBIT (1<<15)
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#define ROUND_ROBIN (1<<14)
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#define ALT_VECTORS (1<<13)
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#define ICACHE_ENABLE (1<<12)
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#define BIG_ENDIAN (1<<7)
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#define DCACHE_ENABLE (1<<2)
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#define PROTECT_ENABLE (1<<0)
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.equ _libnds_argv,0x027FFF70
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@--------------------------------------------------------------------------------
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.section ".init"
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.global _start
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@--------------------------------------------------------------------------------
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.align 4
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.arm
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@--------------------------------------------------------------------------------
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_start:
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@--------------------------------------------------------------------------------
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mov r0, #0x04000000 @ IME = 0;
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str r0, [r0, #0x208]
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@--------------------------------------------------------------------------------
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@ turn the power on for M3
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@--------------------------------------------------------------------------------
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#if SAFE
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ldr r1, =0x8203
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add r0,r0,#0x304
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strh r1, [r0]
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ldr r1, =0x00002078 @ disable TCM and protection unit
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mcr p15, 0, r1, c1, c0
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#endif
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@--------------------------------------------------------------------------------
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@ Protection Unit Setup added by Sasq
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@--------------------------------------------------------------------------------
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@ Disable cache
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ Instruction cache
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mcr p15, 0, r0, c7, c6, 0 @ Data cache
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@ Wait for write buffer to empty
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mcr p15, 0, r0, c7, c10, 4
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ldr r0, =__dtcm_start
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orr r0,r0,#0x0a
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mcr p15, 0, r0, c9, c1,0 @ DTCM base = __dtcm_start, size = 16 KB
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mov r0,#0x20
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mcr p15, 0, r0, c9, c1,1 @ ITCM base = 0 , size = 32 MB
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@--------------------------------------------------------------------------------
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@ Setup memory regions similar to Release Version
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@--------------------------------------------------------------------------------
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@------------------------------------------------------------------------
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@ Region 0 - IO registers
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@------------------------------------------------------------------------
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ldr r0,=( PAGE_64M | 0x04000000 | 1)
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mcr p15, 0, r0, c6, c0, 0
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@------------------------------------------------------------------------
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@ Region 1 - Main Memory
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@------------------------------------------------------------------------
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ldr r0,=( PAGE_4M | 0x02000000 | 1)
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mcr p15, 0, r0, c6, c1, 0
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@------------------------------------------------------------------------
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@ Region 2 - alternate vector base
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@------------------------------------------------------------------------
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#if SAFE
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ldr r0,=( PAGE_4K | 0x00000000 | 1)
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mcr p15, 0, r0, c6, c2, 0
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@------------------------------------------------------------------------
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@ Region 3 - DS Accessory (GBA Cart)
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@------------------------------------------------------------------------
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ldr r0,=( PAGE_128M | 0x08000000 | 1)
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mcr p15, 0, r0, c6, c3, 0
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@------------------------------------------------------------------------
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@ Region 4 - DTCM
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@------------------------------------------------------------------------
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ldr r0,=__dtcm_start
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orr r0,r0,#(PAGE_16K | 1)
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mcr p15, 0, r0, c6, c4, 0
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@------------------------------------------------------------------------
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@ Region 5 - ITCM
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@------------------------------------------------------------------------
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ldr r0,=__itcm_start
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@ align to 32k boundary
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mov r0,r0,lsr #15
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mov r0,r0,lsl #15
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orr r0,r0,#(PAGE_32K | 1)
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mcr p15, 0, r0, c6, c5, 0
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@------------------------------------------------------------------------
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@ Region 6 - System ROM
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@------------------------------------------------------------------------
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ldr r0,=( PAGE_32K | 0xFFFF0000 | 1)
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mcr p15, 0, r0, c6, c6, 0
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@------------------------------------------------------------------------
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@ Region 7 - non cacheable main ram
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@------------------------------------------------------------------------
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ldr r0,=( PAGE_4M | 0x02400000 | 1)
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mcr p15, 0, r0, c6, c7, 0
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@------------------------------------------------------------------------
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@ Write buffer enable
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@------------------------------------------------------------------------
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ldr r0,=0b00000010
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mcr p15, 0, r0, c3, c0, 0
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#endif
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@------------------------------------------------------------------------
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@ DCache & ICache enable
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@------------------------------------------------------------------------
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ldr r0,=0b01000010
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mcr p15, 0, r0, c2, c0, 0
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mcr p15, 0, r0, c2, c0, 1
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@------------------------------------------------------------------------
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@ IAccess
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@------------------------------------------------------------------------
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#if SAFE
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ldr r0,=0x36636633
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mcr p15, 0, r0, c5, c0, 3
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@------------------------------------------------------------------------
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@ DAccess
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@------------------------------------------------------------------------
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ldr r0,=0x36333633
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mcr p15, 0, r0, c5, c0, 2
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#endif
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@------------------------------------------------------------------------
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@ Enable ICache, DCache, ITCM & DTCM
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@------------------------------------------------------------------------
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mrc p15, 0, r0, c1, c0, 0
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#if SAFE
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ldr r1,= ITCM_ENABLE | DTCM_ENABLE | ICACHE_ENABLE | DCACHE_ENABLE | PROTECT_ENABLE
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#else
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ldr r1, =ICACHE_ENABLE|DCACHE_ENABLE|PROTECT_ENABLE
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#endif
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orr r0,r0,r1
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mcr p15, 0, r0, c1, c0, 0
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mov r0, #0x12 @ Switch to IRQ Mode
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msr cpsr, r0
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ldr sp, =__sp_irq @ Set IRQ stack
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mov r0, #0x13 @ Switch to SVC Mode
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msr cpsr, r0
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ldr sp, =__sp_svc @ Set SVC stack
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mov r0, #0x1F @ Switch to System Mode
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msr cpsr, r0
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ldr sp, =__sp_usr @ Set user stack
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#if SAFE
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ldr r1, =__itcm_lma @ Copy instruction tightly coupled memory (itcm section) from LMA to VMA
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ldr r2, =__itcm_start
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ldr r4, =__itcm_end
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bl CopyMemCheck
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ldr r1, =__vectors_lma @ Copy reserved vectors area (itcm section) from LMA to VMA
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ldr r2, =__vectors_start
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ldr r4, =__vectors_end
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bl CopyMemCheck
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ldr r1, =__dtcm_lma @ Copy data tightly coupled memory (dtcm section) from LMA to VMA
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ldr r2, =__dtcm_start
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ldr r4, =__dtcm_end
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bl CopyMemCheck
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bl checkARGV @ check and process argv trickery
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ldr r0, =__bss_start @ Clear BSS section
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ldr r1, =__bss_end
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sub r1, r1, r0
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bl ClearMem
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ldr r0, =__sbss_start @ Clear SBSS section
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ldr r1, =__sbss_end
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sub r1, r1, r0
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bl ClearMem
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ldr r1, =fake_heap_end @ set heap end
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ldr r0, =__eheap_end
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str r0, [r1]
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ldr r0, =_libnds_argv
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@ reset heap base
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ldr r2, [r0,#20] @ newheap base
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ldr r1,=fake_heap_start
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str r2,[r1]
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push {r0}
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ldr r3, =initSystem
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blx r3 @ system initialisation
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ldr r3, =__libc_init_array @ global constructors
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blx r3
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pop {r0}
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ldr r1, [r0,#16] @ argv
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ldr r0, [r0,#12] @ argc
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#endif
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ldr r3, =Main
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blx r3 @ jump to user code
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#if SAFE
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@ If the user ever returns, go back to passme loop
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ldr r0, =ILoop
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ldr r0, [r0]
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ldr r1, =0x027FFE78
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str r0, [r1]
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bx r1
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ILoop:
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b ILoop
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@-------------------------------------------------------------------------------
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@ check for a commandline
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@-------------------------------------------------------------------------------
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checkARGV:
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@-------------------------------------------------------------------------------
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ldr r0, =_libnds_argv @ argv structure
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mov r1, #0
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str r1, [r0,#12] @ clear argc
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str r1, [r0,#16] @ clear argv
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ldr r1, [r0] @ argv magic number
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ldr r2, =0x5f617267 @ '_arg'
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cmp r1, r2
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bxne lr @ bail out if no magic
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ldr r1, [r0, #4] @ command line address
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ldr r2, [r0, #8] @ length of command line
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@ copy to heap
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ldr r3, =__end__ @ initial heap base
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str r3, [r0, #4] @ set command line address
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cmp r2, #0
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subnes r4, r3, r1 @ dst-src
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bxeq lr @ dst == src || len==0 : nothing to do.
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cmphi r2, r4 @ len > (dst-src)
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bhi .copybackward
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.copyforward:
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ldrb r4, [r1], #1
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strb r4, [r3], #1
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subs r2, r2, #1
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bne .copyforward
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b .copydone
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.copybackward:
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subs r2, r2, #1
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ldrb r4, [r1, r2]
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strb r4, [r3, r2]
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bne .copybackward
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.copydone:
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push {lr}
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ldr r3, =build_argv
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blx r3
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pop {lr}
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bx lr
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@-------------------------------------------------------------------------------
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@ Clear memory to 0x00 if length != 0
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@ r0 = Start Address
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@ r1 = Length
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@-------------------------------------------------------------------------------
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ClearMem:
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@-------------------------------------------------------------------------------
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mov r2, #3 @ Round down to nearest word boundary
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add r1, r1, r2 @ Shouldn't be needed
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bics r1, r1, r2 @ Clear 2 LSB (and set Z)
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bxeq lr @ Quit if copy size is 0
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mov r2, #0
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ClrLoop:
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stmia r0!, {r2}
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subs r1, r1, #4
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bne ClrLoop
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bx lr
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@-------------------------------------------------------------------------------
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@ Copy memory if length != 0
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@ r1 = Source Address
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@ r2 = Dest Address
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@ r4 = Dest Address + Length
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@-------------------------------------------------------------------------------
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CopyMemCheck:
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@-------------------------------------------------------------------------------
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sub r3, r4, r2 @ Is there any data to copy?
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@-------------------------------------------------------------------------------
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@ Copy memory
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@ r1 = Source Address
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@ r2 = Dest Address
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@ r3 = Length
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@-------------------------------------------------------------------------------
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CopyMem:
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@-------------------------------------------------------------------------------
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mov r0, #3 @ These commands are used in cases where
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add r3, r3, r0 @ the length is not a multiple of 4,
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bics r3, r3, r0 @ even though it should be.
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bxeq lr @ Length is zero, so exit
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CIDLoop:
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ldmia r1!, {r0}
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stmia r2!, {r0}
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subs r3, r3, #4
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bne CIDLoop
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bx lr
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#endif
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@--------------------------------------------------------------------------------
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.align
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.pool
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.end
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@--------------------------------------------------------------------------------
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#endif
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