properly clear and enable interrupts

2019-01-04 14:54:08 +01:00
parent dfedb739b9
commit b2cdcc65fe
1 changed files with 3 additions and 3 deletions
--- a/Code/render.asm
+++ b/Code/render.asm
@@ -1,4 +1,5 @@
 INCLUDE "hardware.inc"
+INCLUDE "utils.inc"

 RENDER_IN_HBL EQU 0

@@ -126,9 +127,7 @@ ELSE
 	ld a, IEF_VBLANK
 ENDC
 	ld [rIE], a
-	xor a
-	ei
-	ldh [rIF], a
+	ClearAndEnableInterrupts
 	
 	ret

@@ -141,6 +140,7 @@ WaitRender:
 	halt
 	jr WaitRender

+	di
 IF RENDER_IN_HBL != 0
 	; enable only v-blank interrupt and wait for vbl
 	ld a, IEF_VBLANK